1. Field of the Invention
The present invention relates in general to a multi-chip semiconductor package and a method for manufacturing such a package. Particularly, the present Invention relates to a multi-chip semiconductor package and to a method for manufacturing such a package in which semiconductor chips are secured on upper and lower surfaces of a plurality of inner leads of lead frame having no paddle, respectively, by soldering without additional wire bonding process, thereby reducing the thickness of packages due to Increased integration of the element and also simplifying the manufacturing process thereof and reducing the manufacturing cost.
2. Description of the Prior Art
Recently, in correspondence with integration requirement in the semiconductor techinques, there have been several efforts for enclosing as many chips in a limited space as possible. For example, there have been widely used multi-chip semiconductor packages in which different types of memory chips are enclosed in a memory module, thus providing a piggybag type of package.
The known semiconductor chips used in the above type of multi-chip semiconductor package generally have functions of addressing in a Z-direction instead of a RAS(row address strobe) in the memory module or a board level according to a method such as a SOP(small outline package), a SOJ(small outline J-lead package) or a TSOP(thin small outline package) depending upon types thereof, respectively.
A representative example of the known multi-chip semiconductor package of the piggy-bag type will be described in detail in conjunction with FIGS. 1 and 2, as follows.
With reference to FIG. 1 which is a cross sectional view showing a structure of a known LOC (lead on chip) -SOJ(small outline J-lead package) type of semiconductor package, the package has a semiconductor chip 1 which is provided with insulating polyimide layers 2 coated on the upper side surfaces thereof in order that each has a predetermined thickness throughout the whole length and width thereof. The chip 1 includes a plurality of pads 3 each of which is electrically connected to an end of each inner lead 4 of a lead frame through a wire 5 of which opposite ends are connected to the pad 3 and the inner lead 4, respectively. In addition, the chip 1 is covered with an epoxy resin layer 6 by a molding process to cover a predetermined area including the inner leads 4.
After preparing semiconductor packages having the above mentioned construction, one of the semiconductor packages, as an upper package p", is to be superposed on another semiconductor package p' having the same construction as that of the upper package p", thereafter, they are electrically connected to each other by connection of an outer lead 4" of the upper package p", to an outer lead 4' of the lower package p', thereby providing a piggy-back type of multi-chip semiconductor package p. The known multi-chip semiconductor package p can be installed in a memory module or in a board level by a conventional installing method.
However, to accomplish the process for manufacturing the known multi-chip semiconductor package p, the upper package p", should be superposed on the lower package p', the packages p' and p" having been separately manufactured, then electrically connected thereto by connecting the outer leads 4' and 4" of the packages p' and p", to each other, as described above, Moreover, the multi-chip package p is obliged to have substantial thickness owing to a wire loop height of each package p', p", occurring during the wire bonding process and also owing to the thickness of the epoxy resin layer 6 of each package p', p". Thus, the known multi-chip semiconductor package p has disadvantages in that it can not accomplish a desired thickness thereof and it requires a substantially complex process for being manufactured. That is, each package p', p" is previously separately provided, then one of them is superposed upside down on the other in order to result in the multi-chip package p. In addition, the known multi-chip package 10 has two lead frames and lead wires 5, the number of the lead wires 5 will be two times more than that of the leadframes, thereby necessarily increasing the number of required elements. Accordingly, the known multi-chip semiconductor package has another disadvantage in that it is obliged to increase the manufacturing cost due to the required elements.
The known multi-chip semiconductor package necessarily requires lead wires, resulting in generating a noise and making a boosting speed to be substantially slow.